1. Field of the Invention
The present invention relates generally to a demodulation circuit for infrared data. More particularly, the invention relates to a demodulation circuit which can reproduce infrared data and serial data.
2. Description of the Related Art
According to the development of electronic industries in the recent years, data communication between a plurality of electronic equipments has been spreading as a normal technology. Particularly, in case of a portable terminal or notebook PC (personal computer), for which portability is given importance, reduction of weight has been attempted by eliminating an external storage medium, such as a floppy disk drive, an external magnetic disk driven or so forth. Therefore, the function for communicating with other equipments has been the essential function for such type of equipments, such as portable terminal, notebook PC or so forth. Currently, in addition to a serial communication port typically represented by that according to the RS232C standard, an infrared communication port which does not require cable connection, has been equipped as standard component.
As a standard for infrared communication, IrDA (Infrared Data Association) has been standardized. However, this IrDA standard is adapted for opposing communication in one to one basis to encounter a problem in low freedom in the sense of convenience of use. This problem has been resolved by infrared standard called IrBUS established on Jan., 1998. In the portable terminal or notebook PC equipped with the IrBUS, it becomes necessary to effectively realize hardware which also have communication functions in the conventional serial port.
On the other hand, conversion from an infrared ray into an electric signal has been realized by an analog circuit, and has been commercialized by semiconductor manufacturers as infrared modules. Since no standard has been established for the infrared module per se, interfaces with the electrical signal are different in respective companies. For example, in IRDA or IrBUS, an infrared ray in which data is modulated with a given carrier frequency, has been used. The electrical signal output from the infrared modules is reproduced as a digital signal with modulated carrier frequency or as a serial signal from which the carrier frequency is removed. These reproduction signal are different in transfer rate of data to inherently require serial/parallel conversion circuit dedicated thereto upon outputting data with serial/parallel conversion to a bus. Such serial/parallel conversion circuit is referred to as Universal Asynchronous Receiver/Transmitter (UART) to perform sampling of input sampling data at a sampling rate corresponding to a data rate, then to perform serial/parallel conversion and thus to output the data to the bus at the predetermined timing. Therefore, the demodulation circuit of the electric signal requires dedicated circuit specified therefore to inherently cause increasing of the scale of the circuit.
The Circuit construction in the prior art is illustrated in FIG. 14. In FIG. 14, an infrared input 1 receives a signal output from an infrared module receiving an infrared signal according to IrDA standard, for example. A serial input 2 receives a signal (i.e. serial data) output from a serial port, such as RS-232C or so forth or the infrared module receiving the infrared signal according to IrBUS standard. The infrared input 1 is connected to a system bus 6 via an UART 5B after demodulation by a demodulation circuit 4. The serial input 2 is connected to the system bus 6 only via the UART 5A. Here, the demodulation circuit 4 is designed for converting (i.e. demodulating) the infrared signal into the serial data. As can be clear from FIG. 14, when the demodulation circuit 4 receives the serial signal through the serial input 2 and the UART 5B can provide an output, the UART 5A can be eliminated. However, since the infrared input and the serial input have mutually different communication protocol, correct serial/parallel conversion cannot be performed in the UART 5B, and the UART 5B thus cannot output the correct data to the bus unless the signal output from the demodulation circuit can be identified as either the serial data or the infrared data. Namely, unless the signal output from the demodulation circuit can be identified as either the serial data or the infrared data, control by the communication software becomes impossible. Therefore, the UART 5A and 5B respective have dedicated design adapting to respective communication protocol and the user has to manually perform system setting of the protocol of the reception data preliminarily upon reception. The system performs selection of the UART on the basis of the setting and performs control of the communication software.
As a typical demodulation technology of the infrared input, there is a method to perform demodulation of the infrared input by a low pass filtering (LPF) process by means of a Finite Impulse Response (FIR) type digital filter. This method sets a pass-band by a filter coefficient of the digital LPF to reproduce an objective signal. A tap coefficient of the filter and a result of superimposing are processed by respective one bit. Operation timing is shown in FIG. 15. In FIG. 15, an impulse response corresponding to a pulse P1 input from the infrared input terminal 1 is executed by the LPF 9 to obtain a pulse response A. In the similar manner, a pulse response B corresponding to a pulse P2 input from the infrared input terminal 1 and a pulse response C corresponding to a pulse P3 can be obtained. Then, result of superimposing of the pulse responses A to C is reproduced as a demodulated output.
In such method, while it is possible to input the serial data from the infrared input terminal, it is not possible to distinguish whether the infrared data or the serial data is received, from the demodulated output. As shown in FIG. 14, the demodulated output is supplied to the superior information processing system, such as a CPU (not shown) or so forth via a system bus 6 and then data processing is performed.
For example, which both of the infrared data and the serial data are subject to serial-to-parallel (S/P) conversion process, sampling frequencies required for the S/P conversion process are different in both data. Therefore, it becomes necessary to distinguish whether the input signal is the infrared data or the serial data. On the other hand, in case of the infrared data, since error correction, CRC operation or so forth becomes necessary, discrimination of the input signal between the infrared data or the serial data becomes necessary even in this process. Therefore, upon practical use, it becomes necessary to fix whether the infrared data or the serial data is to be used. However, in the foregoing example, since automatic discrimination between the infrared data and the serial data cannot be performed, automatic switching by software cannot take place.
Here, as an example of another conventional demodulation circuit, a circuit construction is shown in FIG. 16, and operational timing is shown in FIG. 17. In this circuit, a method to preliminarily set a photo receiving range of the infrared input and to eliminate the input out of the photo receiving range from a result of the count of the pulse width of the input infrared ray, is employed. In FIG. 16, the infrared input is input to the LPF 9 and the pulse width counting portion 21, and the pulse width of the reception data is counted with a high speed clock. A result of counting of the pulse width is checked as to whether it falls within a predetermined value or not, by a photo reception error judgment portion 22 to perform reproduction of data.
In the timing chart shown in FIG. 17, during a period where the infrared input is xe2x80x9cHxe2x80x9d, counting of the pulse is performed. Then, if a result of counting of the pulse width falls within the photo receiving range, the data is judged as normal, and otherwise output as photo reception error.
In this technology, when the serial data is input to the infrared input, it can be judged as a photo reception error and thus cannot be demodulated correctly. On the other hand, in order to eliminate noise by setting the photo reception range, a photo receiving element having high response characteristics becomes necessary in the infrared input portion. Since an external noise is independently input and has no continuity, discrimination by the demodulated output is possible.
As further prior art, a circuit shown in Japanese Unexamined Patent Publication No. 9-179669 is illustrated in FIG. 18. In the shown prior art, a system is constructed with a CPU 112 performing data processing, an I/O controller 113 performing signal conversion in order to establish connection between the CPU 112 and the external equipment, an interface selection circuit 114 determining an interface to be used according to instruction from the CPU 112 connected to the I/O controller 113, an IR driver illuminating an infrared ray depending upon a transmission signal output from the I/O controller 113, and a system reset circuit 116 generating a reset signal for resetting a system by detecting on-set of power supply by generating a reset signal and supplying the same to the CPU 112.
The I/O controller 113 is constructed with a CPU interface circuit portion 113a establishing connection with the CPU 112, an IR interface circuit portion 113b for generating a transmission signal for driving the IR driver 115, a serial interface circuit portion 113c for generating the transmission signal for driving the serial driver, a switch for selecting either the IR interface circuit portion 113b or the serial interface circuit portion 113c, and a switch selection circuit portion 113e for controlling the switch. The interface selection circuit 114 generates a selection signal Tc for selecting either of the IR interface circuit portion 113b or the serial interface circuit 113c depending upon a selection command supplied from the CPU 112 to supply to the I/O controller 113.
The shown technology is adapted to permit external control for selecting either the infrared data or the serial data upon reception of the infrared data and the serial data, and does not permit discrimination between the serial data and the infrared data from the received data.
A first problem to be encountered in the prior art set forth above is absence of effective means which can demodulate both of the infrared data input and the serial data input and can discriminate which of the infrared data or the serial data is input. A second problem is to cause the requirement of two UART in the system for the reason that the first problem cannot be solved, which causes increasing of the circuit scale and power consumption. A third problem is that a device having high response characteristics becomes necessary in the infrared ray receiving portion. In this respect, the photo reception element to be employed has to have a photo receiving characteristics falling within a frequency range of photo receiving, and a difference of delay period due to transition response falls within a given value.
It is therefore an object of the present invention to provide a demodulation circuit which can input and output both of a serial data and an infrared data and can discriminate a received data between the serial data and the infrared data.
According to an aspect of the present invention, a demodulation circuit for inclusively receiving an infrared data and a serial data and outputting a decoded signal, comprises:
edge detecting means for detecting an edge of the infrared data and outputting an edge detection signal;
AND means for deriving AND of the edge detection signal and the serial data;
low-pass filter means for initiating a filter operation in response to an output of the AND means and outputting an operation execution signal indicative of a filter operation period preliminarily determined by a total tap number signal of a preliminarily input digital filter and a demodulation signal as a filter process output; and
data discrimination means for discriminating between demodulation of the infrared data and demodulation of the serial data depending upon the operation execution signal and outputting a result of discrimination.
The operation execution signal may be a pulse from completion of inputting of an input signal of the low-pass filter to completion of the filter operation. On the other hand, the data discrimination means may compare number of times of tap calculation of a filter executed during a predetermined period from initiation of outputting of a demodulated signal from the low-pass filter and a preliminarily set number of times to output the result of discrimination depending upon a result of comparison.
In the preferred construction, the low-pass filter means may comprises:
a first m-bit selection circuit taking a first fixed value as one input and controlled by the output signal of the AND means, wherein m is an integer greater than or equal to two;
an m-bit flip-flop taking an output of the first m-bit selection means as input;
a first comparator circuit for comparing an output of the m-bit flip-flop and a second fixed value;
an m-bit adder circuit adding an output of the first comparator circuit to a least significant bit of data output of the m-bit flip-flop;
a second comparator circuit comparing the data output of the m-bit flip-flop and a total tap number of the filter;
a second m-bit selection means taking an output of the m-bit adder and a third fixed value as inputs, controlled by an output of the second comparator circuit and outputting to the other input of the first m-bit selection circuit; and
third comparator circuit comparing the output of the m-bit flip-flop and an arbitrary fixed value,
output signal of the first comparator circuit being output as the operation execution signal, the output signal of the first comparator circuit being output from a demodulation output terminal.
In the alternative, the low-pass filter means may comprise:
a first m-bit selection circuit taking a first fixed value as one input and controlled by the output signal of the AND means, wherein m is an integer greater than or equal to two;
an m-bit flip-flop taking an output of the first m-bit selection means as data input;
a first comparator circuit for comparing a data output of the m-bit flip-flop and a second fixed value;
an m-bit adder circuit adding an output of the first comparator circuit to a least significant bit of data output of the m-bit flip-flop;
a second comparator circuit comparing the data output of the m-bit flip-flop and a total tap number of the filter;
a second m-bit selection means taking an output of the m-bit adder and a third fixed value as inputs, controlled by an output of the second comparator circuit and outputting to the other input of the first m-bit selection circuit; and
an AND circuit deriving an AND of the output of the second comparator circuit and an inverted output of the OR means,
the output signal of the AND circuit being output as the operation execution signal and the output signal of the first comparator circuit being output through a demodulation output terminal.
In the further alternative, the low-pass filer may comprise:
an m-bit selection circuit having three inputs and taking first and second fixed values as inputs;
an m-bit flip-flop taking an output of the m-bit selection means as data input;
a first comparator circuit for comparing a data output of the m-bit flip-flop and a third fixed value;
an m-bit adder circuit adding an output of the first comparator circuit to a least significant bit of data output of the m-bit flip-flop;
a second comparator circuit comparing the data output of the m-bit flip-flop and a total tap number of the filter; and
a third comparator circuit taking the output of the m-bit flip-flop and the arbitrary fixed value as inputs,
the m-bit selection circuit being controlled by the output of the OR means and the output of the second comparator circuit to output the output signal of the third comparator circuit as the operation execution signal, and the output of the first comparator circuit being output from a demodulation output terminal.
In the still further alternative, the low-pass filer may comprise:
a third m-bit selection circuit having three inputs and taking first and second fixed values as inputs;
an m-bit flip-flop taking an output of the third m-bit selection means as data input;
a first comparator circuit for comparing a data output of the m-bit flip-flop and a third fixed value;
an m-bit adder circuit adding an output of the first comparator circuit to a least significant bit of data output of the m-bit flip-flop;
a second comparator circuit comparing the data output of the m-bit flip-flop and a total tap number of the filter; a third comparator circuit taking the output of the m-bit flip-flop and the arbitrary fixed value as inputs, and
an AND circuit deriving an AND of the output of the second comparator circuit and an inverted output of the OR means,
the m-bit selection circuit being controlled by the output of the OR means and the output of the second comparator circuit, the output of the AND circuit being output as the operation execution signal, and the output signal of the first comparator circuit being output through a demodulation output terminal.
Then, the least significant bit of the first fixed value may be set xe2x80x9c1xe2x80x9d, all bits of the first fixed value other than the least significant bit are set xe2x80x9c0xe2x80x9d, all bits of the second and third fixed values may be set xe2x80x9c0xe2x80x9d, and the arbitrary fixed value may be set greater than or equal to xe2x80x9c2xe2x80x9d, and the m may be set at a value derived by rounding a logarithm of 2 of total tap number into an integer.
Also, the data discrimination means may have an AND circuit taking the operation execution signal and a reference timing signal externally input at a preliminarily set reference timing, and an output signal of the AND circuit is output as the discrimination result signal. The data discrimination means may also be supplied a reference timing signal externally input at a preliminarily set reference timing to a holding terminal and is supplied the operation execution signal to an enabling terminal, and may have a counter for counting a predetermined clock signal, for outputting an output signal of the counter as the discrimination result signal.
In the operation of the present invention, the edge detection circuit detects the edge of an infrared input and the OR of the edge signal and the serial data is taken by the OR circuit. The OR output and a total tap number signal are input to the LPF. The LPF has a function for outputting the demodulation output signal and the operation execution signal. By the operation execution signal, demodulation of the infrared input and demodulation of the serial input are discriminated by the data discrimination circuit. By this, the UART for reproducing the infrared data and the serial data is not required separately and can be made common.